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82504 jo im no.7854-1/20 ver.1.04 d2702 LC87F71C8A overview the LC87F71C8A is an 8-bit single chip microcontroller with the following on-chip functional blocks : ? cpu : operable at a minimum bus cycle time of 100ns ? 128k-bytes flash rom (on-board rewritable) ? on-chip ram : 4096-bytes ? lcd controller/driver ? 16-bit timer/counters (can be divided into 8-bit units) ? 16-bit timer (can be divided into 8- bit timers, 8-bit timer can be pwm) ? four 8-bit timer with prescalers ? timer for use as date/time clock ? synchronous serial i/o port (with automatic bl ock transmit/receive function) ? asynchronous/synchronous serial i/o port ? two sets of 12-bit pwm ? 12-channel 8-bit ad converter ? high-speed clock counter ? system clock divider ? small signal detector ? 19-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features flash rom ? single 5v power supply, on-board writable ? block erase in 128-byte units ? 131072 8-bits (LC87F71C8A) random access memory (ram) ? 4096 9-bits (LC87F71C8A) minimum bus cycle time ? 100ns (10mhz) note : the bus cycle time indicates rom read time. ordering number : enn7854 cmos ic from 128k-byte, ram 4096-byte on chip 8-bit 1-chip microcontroller
LC87F71C8A no.7854-2/20 minimum instruction cycle time ? 300ns (10mhz) ports ? input/output ports data direction programmable for each bit individually : 20 (p1n, p70 to p73, p8n) data direction programmable in nibble units : 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) ? input ports : 2 (xt1, xt2) ? output ports : 2 (pwm2, pwm3) ? lcd ports segment output : 32 (s00 to s15, s24 to s39) common output : 4 (com0 to com3) bias terminals for lcd driver 3 (v1 to v3) other functions input/output ports : 32 (pan, pbn, pdn, pen) input ports : 7 (pln) ? oscillator pins : 2 (cf1, cf2) ? reset pin : 1 ( res ) ? power supply : 6 (v ss 1 to 3, v dd 1 to 3) lcd controller ? seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) ? segment output and common output can be switched to general purpose input/output ports. small signal detection (mic signals etc) ? counts pulses with the level whic h is greater than a preset value ? 2-bit counter timer ? timer 0 : 16-bit timer/counter with capture register mode 0 : 2-channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register mode 3 : 16-bit counter with 16-bit capture register ? timer 1 : pwm/16-bit timer with toggle output function mode 0 : 2-channel 8-bit timer with 8-bit prescaler (with toggle output) mode 1 : 2-channel 8-bit pwm with 8-bit prescaler mode 2 : 16-bit timer with 8-bit prescaler (with toggle ou tput) toggle output from lower 8-bits is also possible. mode 3 : 16-bit timer with 8-bit prescaler (with togg le output) lower order 8-bits can be used as pwm. ? timer 4 : 8-bit timer with 6-bit prescaler ? timer 5 : 8-bit timer with 6-bit prescaler ? timer 6 : 8-bit timer with 6-bit prescaler (with toggle output) ? timer 7 : 8-bit timer with 6-bit prescaler (with toggle output) ? base timer 1. the clock signal can be selected from any of the following : sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2. interrupts of five different time intervals are possible. high speed clock counter ? countable up to 20mhz clock (when using 10mhz main clock) ? real time output
LC87F71C8A no.7854-3/20 serial interface ? sio0 : 8-bit synchronous serial interface 1. lsb first/msb first is selectable 2. internal 8-bit baud-rate generator (fastest clock period 4/3 tcyc) 3. consecutive automatic data communication (1 to 256-bits) ? sio1 : 8-bit asynch ronous/synch ronous serial interface mode 0 : synchronous 8-bit serial i o (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1 : asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tcyc) mode 2 : bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3 : bus mode 2 (start detection, 8 data bits, stop detection) ad converter ? 8-bits 12-channels pwm ? two sets of 12-bit periodic variable pwm remote control receiver circuit (con nected to p73/int3/t0in terminal) ? noise rejection function (noise rejection filter?s time constant can be selected from 1/32/128 tcyc) watchdog timer ? the watching time period is determined by an external rc. ? watchdog timer can produce interrupt or system reset interrupts : 19 sources, 10 vectors 1. three priority (low, high and highes t) multiple interrupts are supported. during interrupt handling, an equal or lowe r priority interrupt request is postponed. 2. if interrupt requests to two or more vector addre sses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, th e vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/mic/t6/t7 10 0004bh h or l port 0/t4/t5/pwm2, 3 ? priority level : x>h>l ? for equal priority levels, vector with lowest address takes precedence. subroutine stack levels : 2048 levels max. stack is located in ram. multiplication and division ? 16-bit 8-bit (executed in 5 cycles) ? 24-bit 16-bit (12 cycles) ? 16-bit 8-bit (8 cycles) ? 24-bit 16-bit (12 cycles)
LC87F71C8A no.7854-4/20 oscillation circuits ? on-chip rc oscillation for system clock use. ? cf oscillation for system clock use. (rf built in, rd external) ? crystal oscillation low speed system clock use. (rf built in, rd external) ? on-chip frequency variable rc oscillation circuit for system clock use. system clock divider ? low power consumption operation is available ? minimum instruction cycle time (300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s can be switched by program (when using 10mhz main clock) standby function ? halt mode halt mode is used to reduce power consumption. during the halt mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1. oscillation circuits are not stopped automatically. 2. released by the system reset or interrupts. ? hold mode hold mode is used to reduce power consumption. program execution and peripheral circuits are stopped. 1. cf, rc and crystal oscillation circuits stop automatically. 2. released by any of the following conditions. 1. low level input to the reset pin 2. specified level input to one of int0, int1, int2 3. port 0 interrupt ? x?tal hold mode x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits excep t the base timer are stopped. 1. cf and rc oscillation circuits stop automatically. 2. crystal oscillator operation is kept in its state at hold mode inception. 3. released by any of the following conditions 1. low level input to the reset pin 2. specified level input to one of int0, int1, int2 3. port 0 interrupt 4. base-timer interrupt package ? qfp80 ? tqfp80 development tools ? evaluation chip : lc876091 ? emulator : eva62s + ecb876600c (evaluation chip board) + sub877100 + pod80qfp (14 14) or pod80sqfp : ice-b877300 + sub877100 + pod80qfp (14 14) or pod80sqfp ? flash rom write adapter : w87f71256qf or w87f71256sq same package and pin assignment as mask rom version. 1. lc877100 series options can be set using flash rom data. thus the board used for mass production can be used for debugging and evaluation without modifications. 2. if the program for the mask rom version is used, th e usable rom/ram capacity is the same as the mask rom version.
LC87F71C8A no.7854-5/20 package dimensions package dimensions unit : mm unit : mm 3255 3298 pin assignment com0/pl0 com1/pl1 com2/pl2 com3/pl3 pwm2 v ss 3 v dd 3 pwm3 p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 v1/pl4 v2/pl5 v3/pl6 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s15/pb7 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v ss 2 v dd 2 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 s0/pa0 p73/int3/t0in p72/int2/t0in p71/int1/t0hcp/an9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LC87F71C8A top view
LC87F71C8A no.7854-6/20 system block diagram interrupt control stand-by control ir pla rom pc bus interface port 0 port 1 sio0 sio1 base timer lcd controller int0 to 3 noise rejection filter port 7 port 8 adc weak signal detector acc b register c register psw rar ram stack pointer watch dog timer alu timer 4 timer 5 timer 6 timer 7 timer 0 (high-speed clock counter) timer 1 clock generator cf rc mrc x?tal pwm
LC87F71C8A no.7854-7/20 pin description pin name i/o function option v ss 1, v ss 2, v ss 3 - power supply (-) no v dd 1, v dd 2, v dd 3 - power supply (+) no port 0 p00 to p07 i/o ? 8-bit input/output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt ? other pin functions p05 : system clock output p06 : timer 6 toggle output p07 : timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit input/output port ? data direction programmable for each bit ? use of pull-up resistor can be specified for each bit individually ? other pin functions p10 : sio0 data output p11 : sio0 data input or bus input/output p12 : sio0 clock input/output p13 : sio1 data output p14 : sio1 data input or bus input/output p15 : sio1 clock input/output p16 : timer 1 pwml output p17 : timer 1 pwmh output/buzzer output yes ? 4-bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit individually ? other functions p70 : int0 input/hold release input/time r 0l capture input/output for watchdog timer p71 : int1 input/hold release input/timer 0h capture input p72 : int2 input/hold release input/timer 0 event input/timer 0l capture input p73 : int3 input (noise rejection filter attac hed) /timer 0 event input/timer 0h capture input ad input port : an8 (p70), an9 (p71) ? interrupt detection selection rising falling rising and falling h level l level int0 int1 int2 int3 yes yes yes yes yes yes yes yes no no yes yes yes yes no no yes yes no no port 7 p70 to p73 i/o no port 8 p80 to p87 i/o ? 8-bit input/output port ? input/output can be specified for each bit individually ? other functions : ad input port : an0 to an7 small signal detector input port : micin (p87) no s0/pa0 to s7/pa7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pa) no s8/pb0 to s15/pb7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pb) no s24 /pd0 to s31/pd7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pd) no s32/pe0 to s39/pe7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pe) no com0/pl0 to com3/pl3 i/o ? common output for lcd ? can be used as general purpose input port (pl) no v1/pl4 to v3/pl6 i/o ? lcd output bias power supply ? can be used as general purpose input port (pl) no pwm2 o ? pwm2 output no pwm3 o ? pwm3 output no continued on next page.
LC87F71C8A no.7854-8/20 continued from preceding page. pin name i/o function option res i reset terminal no xt1 i ? input for 32.768khz crystal oscillation ? other functions : general purpose input port ad input port : an10 ? when not in use, connect to v dd 1 no xt2 i/o ? output for 32.768khz crystal oscillation ? other functions : general purpose input port ad input port : an11 ? when not in use, set to oscillation mode and leave open no cf1 i input terminal for ceramic oscillator no cf2 o output terminal for ceramic oscillator no port output configuration port form and pull-up resistor options are shown in the following table. port status can be read even when port is set to output mode. terminal option applies to : option output format pull-up resistor 1 cmos programmable (note 1) p00 to p07 each bit 2 nch-open drain none 1 cmos programmable p10 to p17 each bit 2 nch-open drain programmable p70 ? none nch-open drain programmable p71 to p73 ? none cmos programmable p80 to p87 ? none nch-open drain none s0/pa0 to 15/pb7 s24/pd0 to 39/pe7 ? none cmos programmable com0/pl0 to com3/pl3 ? none input only none v1/pl4 to v3/pl6 ? none input only none pwm2, pwm3 ? none cmos none xt1 ? none input only none xt2 ? none output for 32.768khz crystal oscillation none note 1 : attachment of port 0 programmable pull-up resistors is controllable in nibble units (p00 to 03, p04 to 07). * note 1 : connect as follows to reduce noise on v dd . v ss 1, v ss 2 and v ss 3 must be connected together and grounded. * note 2 : the power supply fo r the internal memory is v dd 1 but it uses the v dd 2, v dd 3 as the power supply for ports. when the v dd 2 is not backed up, the port level does not become "h" even if the port latch is in the "h" level. therefore, when the v dd 2 is not backed up and the port latc h is "h" level, the port level is unstable in the hold mode, and the back up time beco mes shorter because the th rough current runs from v dd to gnd in the input buffer. if v dd 2 is not backed up, output "l" by the program or pull the port to "l" by the external circuit in the hold mode so that the port level becomes "l" level and unnecessary current consumption is prevented. back-up capacitor *2 power supply lsi v dd 1 v dd 2 v dd 3 v ss 3 v ss 2 v ss 1
LC87F71C8A no.7854-9/20 absolute maximum ratings / ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1 = v dd 2 = v dd 3 -0.3 +6.5 supply voltage for lcd vlcd v1/pl4, v2/pl5, v3/pl6 v dd 1 = v dd 2 = v dd 3 -0.3 v dd input voltage v i port l xt1, xt2, cf1, res -0.3 v dd +0.3 input/output voltage v io ? port 0, 1, 7, 8 ? port a, b, d, e ? pwm2, pwm3 -0.3 v dd +0.3 v ioph(1) port 0, 1 ? cm os output selected ? current at each pin -10 ioph(2) port 71, 72, 73 current at each pin -3 peak output current ioph(3) port a, b, d, e, pwm2 pwm3 current at each pin -5 ioah(1) port 0, 1, pwm2, pwm3 total of all pins -40 ioah(2) port 30, 31 total of all pins -10 ioah(3) port 7 total of all pins -5 ioah(4) port a, b total of all pins -25 high level output current total output current ioah(5) port d, e total of all pins -25 iopl(1) port 0, 1 current at each pin 20 iopl(2) port 7,8 current at each pin 5 peak output current iopl(3) port a, b, d, e, pwm2, pwm3 current at each pin 15 ioal(1) port 0, 1, pwm2, pwm3 total of all pins 60 ioal(2) port 7, 8 total of all pins 20 ioal(3) port a, b total of all pins 40 low level output current total output current ioal(4) port d, e total of all pins 40 ma qfp80 453 maximum power consumption pd max tqfp80 ta = -20 to +70c 351 mw operating temperature range topr -20 70 storage temperature range tstg -55 125 c
LC87F71C8A no.7854-10/20 recommended operating range / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit v dd (1) 0.294 s tcyc 200 s 4.5 5.5 operating supply voltage range v dd (2) v dd 1 = v dd 2 = v dd 3 0.735 s tcyc 200 s 3.0 5.5 supply voltage range in hold mode vhd v dd 1 keep ram and register data in hold mode. 2.0 5.5 v ih (1) ? port 0, 8 ? port a, b, d, e, l output disable 3.0 to 5.5 0.3v dd +0.7 v dd v ih (2) ? port 1 ? port 71, 72, 73 ? p70 port input/interrupt output disable 3.0 to 5.5 0.3v dd +0.7 v dd v ih (3) p87 small signal input output disable 3.0 to 5.5 0.75v dd v dd v ih (4) port 70 watchdog timer output disable 3.0 to 5.5 0.9v dd v dd input high voltage v ih (5) xt1, xt2, cf1, res 3.0 to 5.5 0.75v dd v dd v il (1) ? port 0, 8 ? port a, b, d, e, l output disable 3.0 to 5.5 v ss 0.15v dd +0.4 v il (2) ? port 1 ? port 71, 72, 73 ? p70 port input/interrupt output disable 3.0 to 5.5 v ss 0.1v dd +0.4 v il (3) port 87 small signal input output disable 3.0 to 5.5 v ss 0.25v dd v il (4) port 70 watchdog timer output disable 3.0 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (5) xt1, xt2, cf1, res 3.0 to 5.5 v ss 0.25v dd v 4.5 to 5.5 0.294 200 operation cycle time tcyc 3.0 to 5.5 0.735 200 s 4.5 to 5.5 0.1 10 ? cf2 open ? system clock divider : 1/1 ? external clock duty = 50 5% 3.0 to 5.5 0.1 4 4.5 to 5.5 0.2 20 external system clock frequency fexcf(1) cf1 ? cf2 open ? system clock divider : 1/2 3.0 to 5.5 0.2 8 fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5 to 5.5 10 fmcf(2) cf1, cf2 4mhz ceramic resonator oscillation refer to figure 1 3.0 to 5.5 4 fmrc rc oscillation 3.0 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 3.0 to 5.5 50 mhz oscillation frequency range (note 1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 3.0 to 5.5 32.768 khz note 1 : the parts value of oscillation circuit is shown in table 1 and table 2.
LC87F71C8A no.7854-11/20 electrical characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit i ih (1) ? port 0, 1, 7, 8 ? port a, b, d, e, l ? pwm2, pwm3 ? output disabled ? pull-up resister off. ? v in = v dd (including off state leak current of the output tr.) 3.0 to 5.5 1 i ih (2) res v in = v dd 3.0 to 5.5 1 i ih (3) xt1, xt2 when configured as an input port v in = v dd 3.0 to 5.5 1 i ih (4) cf1 v in = v dd 3.0 to 5.5 15 4.5 to 5.5 4.2 8.5 15 high level input current i ih (5) p87/an7/micin small signal input v in = vbis+0.5v (vbis : bias voltage) 3.0 to 4.5 1.5 5.5 10 i il (1) ? port 0, 1, 7, 8 ? port a, b, d, e, l ? pwm2, pwm3 ? output disabled ? pull-up resister off. ? v in = v ss (including off state leak current of the output tr.) 3.0 to 5.5 -1 i il (2) res v in = v ss 3.0 to 5.5 -1 i il (3) xt1, xt2 when configured as an input port v in = v ss 3.0 to 5.5 -1 i il (4) cf1 v in = v ss 3.0 to 5.5 -15 4.5 to 5.5 -15 -8.5 -4.2 low level input current i il (5) p87/an7/micin small signal input v in = vbis-0.5v (vbis : bias voltage) 3.0 to 4.5 -10 -5.5 -1.5 a v oh (1) i oh = -1.0ma 4.5 to 5.5 v dd -1 v oh (2) port 0, 1 cmos output option i oh = -0.1ma 3.0 to 5.5 v dd -0.5 v oh (3) port 7 i oh = -0.4ma 3.0 to 5.5 v dd -1 v oh (4) i oh = -1.0ma 4.5 to 5.5 v dd -1 high level output voltage v oh (5) port a, b, d, e pwm2, pwm3 i oh = -0.1ma 3.0 to 5.5 v dd -0.5 v ol (1) i ol = 10ma 4.5 to 5.5 1.5 v ol (2) port 0, 1 i ol = 1.6ma 3.0 to 5.5 0.4 v ol (3) i ol = 1ma 4.5 to 5.5 0.4 v ol (4) port 7, 8 i ol = 0.5ma 3.0 to 5.5 0.4 v ol (5) i ol = 8ma 4.5 to 5.5 1.5 low level output voltage v ol (6) port a, b, d, e, pwm2, pwm3 i ol = 1.4ma 3.0 to 5.5 0.4 vodls s0 to s15, s24 to s39 i o = 0ma vlcd, 2/3vlcd, 1/3vlcd level output refer to figure 8 3.0 to 5.5 0 0.2 lcd output voltage regulation vodlc com0 to com3 i o = 0ma vlcd, 2/3vlcd, 1/2vlcd 1/3vlcd level output refer to figure 8 3.0 to 5.5 0 0.2 v rlcd(1) resistance per one bias resistor refer to figure 8 3.0 to 5.5 60 lcd bias resistor rlcd(2) ? resistance per one bias resistor ? 1/2r mode refer to figure 8 3.0 to 5.5 30 4.5 to 5.5 15 40 70 resistance of pull-up mos tr. rpu ? port 0, 1, 7 ? port a, b, d, e v oh = 0.9v dd 3.0 to 5.5 25 70 150 k ? vhis(1) ? port 1, 7 ? res 3.0 to 5.5 0.1v dd hysterisis voltage vhis(2) port 87 small signal input 3.0 to 5.5 0.1v dd v pin capacitance cp all pins ? all other terminals connected to v ss . ? f = 1mhz ? ta = 25c 3.0 to 5.5 10 pf input sensitivity vsen port 87 small signal input 3.0 to 5.5 0.12v dd vp-p
LC87F71C8A no.7854-12/20 serial input/output characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit cycle time tsck(1) 4/3 tsckl(1) 2/3 low level pulse width tsckla(1) 2/3 tsckh(1) 2/3 high level pulse width tsckha(1) sck0 (p12) refer to figure 6 3.0 to 5.5 3 cycle time tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1 (p15) refer to figure 6 3.0 to 5.5 1 cycle time tsck(3) 4/3 tcyc tsckl(3) 1/2 low level pulse width tsckla(2) 3/4 tsckh(3) 1/2 high level pulse width tsckha(2) sck0 (p12) ? cmos output ? refer to figure 6 3.0 to 5.5 2 tsck cycle time tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1 (p15) ? cmos output ? refer to figure 6 3.0 to 5.5 1/2 tsck 4.5 to 5.5 0.03 data set-up time tsdi 3.0 to 5.5 0.1 4.5 to 5.5 0.03 serial input data hold time thdi si0 (p11), si1 (p14), sb0 (p11), sb1 (p14) ? measured with respect to si0clk leading edge. ? refer to figure 6 3.0 to 5.5 0.1 4.5 to 5.5 1/3 tcyc +0.05 serial output output delay time tddo so0 (p10), so1 (p13), sb0 (011), sb1 (p14) ? when port is open drain : time delay form sioclk trailing edge to the so data change ? refer to figure 6 3.0 to 5.5 1/3 tcyc +0.25 s
LC87F71C8A no.7854-13/20 pulse input conditions / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) int0 (p70), int1 (p71), int2 (p72) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 3.0 to 5.5 1 tpih(2) tpil(2) int3 (p73) (noise rejection ratio is 1/1.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 3.0 to 5.5 2 tpih(3) tpil(3) int3 (p73) (noise rejection ratio is 1/32.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 3.0 to 5.5 64 tpih(4) tpil(4) int3 (p73) (noise rejection ratio is 1/128.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 3.0 to 5.5 256 tpil(5) tpil(5) micin (p87) ? condition that signal is accepted to small signal detection counter. 3.0 to 5.5 1 tcyc high/low level pulse width tpil(6) res ? condition that reset is accepted 3.0 to 5.5 200 s ad converter characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note2) 3.0 to 5.5 1.5 lsb 4.0 to 5.5 15.62 (tcyc = 0.488 s) 97.92 (tcyc = 3.06 s) ad conversion time = 32 tcyc (adcr2 = 0) (note 3) 3.0 to 5.5 23.52 (tcyc = 0.735 s) 97.92 (tcyc = 3.06 s) 4.5 to 5.5 18.82 (tcyc = 0.294 s) 97.92 (tcyc = 1.53 s) conversion time tcad ad conversion time = 64 tcyc (adcr2 = 1) (note 3) 3.0 to 5.5 47.04 (tcyc = 0.735 s) 97.92 (tcyc = 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain = v dd 3.0 to 5.5 1 analog port input current iainl an0 (p80) to an7 (p87) an8 (p70) an9 (p71) an10 (xt1) an11 (xt2) vain = v ss 3.0 to 5.5 -1 a note 2 : absolute precision does no t include quantizing error (1/2 lsb). note 3 : conversion time means time from executing ad conversion instruction to loading complete digital value to register.
LC87F71C8A no.7854-14/20 current dissipation characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit iddop(1) ? fmcf = 10mhz ce ramic resonator oscillation ? fsx?tal = 32.768khz crystal oscillation ? system clock : cf 10mhz oscillation ? frequency variable rc oscillation stopped ? internal rc oscillation stopped. ? divider : 1/1 4.5 to 5.5 16 35 iddop(2) ? cf1 = 20mhz external clock ? fsx?tal = 32.768khz crystal oscillation ? system clock : cf1 oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/2 4.5 to 5.5 17 36 iddop(3) 4.5 to 5.5 7 21 iddop(4) ? fmcf = 4mhz ceramic resonator oscillation ? fsx?tal = 32.768khz crystal oscillation ? system clock : cf 4mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/1 3.0 to 4.5 3 13 iddop(5) 4.5 to 5.5 1.5 11 iddop(6) ? fmcf = 0hz (no oscillation) ? fsx?tal = 32.768khz crystal oscillation ? frequency variable rc oscillation stopped ? system clock : rc oscillation ? divider : 1/2 3.0 to 4.5 0.8 7 iddop(7) 4.5 to 5.5 2.5 13 iddop(8) ? fmcf = 0hz (no oscillation) ? fsx?tal = 32.768khz crystal oscillation ? internal rc oscillation stopped. ? system clock : 1mhz with frequency variable rc oscillation ?divider : 1/2 3.0 to 4.5 1.8 9 ma iddop(9) 4.5 to 5.5 80 450 current consumption during normal operation (note 4) iddop(10) v dd 1 = v dd 2 = v dd 3 ? fmcf = 0hz (no oscillation) ? fsx?tal = 32.768khz crystal oscillation ? system clock : 32.768khz ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/2 3.0 to 4.5 35 250 a iddhalt(1) halt mode ? fmcf = 10mhz ceramic resonator oscillation ? fsx?tal = 32.768khz crystal oscillation ? system clock : cf 10mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/1 4.5 to 5.5 4.6 12 iddhalt(2) halt mode ? cf1 = 20mhz external clock ? fsx?tal = 32.768khz crystal oscillation ? system clock : cf1 oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/2 4.5 to 5.5 5.1 13 iddhalt(3) 4.5 to 5.5 2.2 6 current consumption during halt mode (note 4) iddhalt(4) v dd 1 = v dd 2 = v dd 3 halt mode ? fmcf = 4mhz ceramic resonator oscillation ? fsx?tal = 32.768khz crystal oscillation ? system clock : cf 4mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/1 3.0 to 4.5 1.0 5 ma continued on next page.
LC87F71C8A no.7854-15/20 continued from preceding page. limits parameter symbol pins conditions v dd [v] min typ max unit iddhalt(5) 4.5 to 5.5 600 1600 iddhalt(6) halt mode ? fmcf = 0hz (oscillation stop) ? fsx?tal = 32.768khz crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stopped ? divider : 1/2 3.0 to 4.5 350 1300 iddhalt(7) 4.5 to 5.5 1500 3600 iddhalt(8) halt mode ? fmcf = 0hz (no oscillation) ? fsx?tal = 32.768khz crystal oscillation ? internal rc oscillation stopped. ? system clock : 1mhz with frequency variable rc oscillation ?divider : 1/2 3.0 to 4.5 1250 3300 iddhalt(9) 4.5 to 5.5 25 100 current consumption during halt mode (note 4) iddhalt(10) v dd 1 = v dd 2 = v dd 3 halt mode ? fmcf = 0hz (oscillation stop) ? fsx?tal = 32.768khz crystal oscillation ? system clock : 32.768khz ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider : 1/2 3.0 to 4.5 12 60 a iddhold(1) 4.5 to 5.5 0.1 25 current consumption during hold mode iddhold(2) v dd 1 hold mode ? cf1 = v dd or open (when using external clock) 3.0 to 4.5 0.03 20 iddhold(3) 4.5 to 5.5 20 90 current consumption during date/time clock hold mode iddhold(4) v dd 1 date/time clock hold mode ? cf1 = v dd or open (when using external clock) ? fmx?tal = 32.768khz crystal oscillation 3.0 to 4.5 8 50 a note 4 : the currents through the output transistors and the pull-up mos transistors are ignored. f-rom write characteristics / ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit on-board write current iddf(1) v dd 1 ? 128-byte write ? including erase current 4.5 to 5.5 30 65 ma write cycle time tfw(1) ? 128-byte write ? including erase current ? not including time to prepare 128-byte data 4.5 to 5.5 5 10 ms main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 [pf] c2 [pf] rd1 [ ? ] operating supply voltage range [v] typ [ms] max [ms] notes cstls10m0g53-b0 (15) (15) 100 4.5 to 5.5 0.04 0.2 built-in c1, c2 10mhz murata cstce10m0g52-r0 (10) (10) 100 4.5 to 5.5 0.04 0.2 built-in c1, c2 cstls4m00g56-b0 (47) (47) 470 3.0 to 5.5 0.13 0.65 built-in c1, c2 4mhz murata cstcr4m00g55-r0 (39) (39) 0 3.0 to 5.5 0.13 0.65 built-in c1, c2 the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 4)
LC87F71C8A no.7854-16/20 subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 2. subsystem clock oscillation circu it characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 [pf] c4 [pf] rf [ ? ] rd2 [ ? ] operating supply voltage range [v] typ [s] max [s] notes 32.768khz seiko epson mc-306 15 15 open 620k 3.0 to 5.5 1.1 3.0 applicable cl value = 12.5pf the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after rel easing the hold mode. (refer to figure 4) notes : since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1 0.5v dd
LC87F71C8A no.7854-17/20 reset time and oscillation stable time hold release signal and oscillation stable time figure 4 oscillation stabilizing time v dd limit powe r res internal rc resonato r cf1, cf2 xt1, xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution mode v dd 0v internal rc resonato r cf1, cf2 xt1, xt2 operation mode hold release without hold release hold release signal valid tmscf tmsxtal hold halt
LC87F71C8A no.7854-18/20 figure 5 reset circuit figure 6 serial input/output wave form c res v dd r res res (note) select c res and r res value to assure that at least 200 s reset time is generated after the v dd becomes higher than the minimum operating voltage. siocl k datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) siocl k datain dataout tsck tsckl tsckh tsdi thdi tddo siocl k datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
LC87F71C8A no.7854-19/20 figure 7 pulse input timing figure 8 lcd bias resistor tpil tpih rlcd rlcd rlcd v dd vlcd sw : on (vlcd = v dd ) 2/3vlcd 1/2vlcd 1/3vlcd gnd sw : on/off (programmable) rlcd rlcd rlcd rlcd rlcd rlcd rlcd
LC87F71C8A no.7854-20/20 ps

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